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d2612hk/12512hkim 20120112-s00001 no.a0956-1/27 http://onsemi.com semiconductor components industries, llc, 2013 may, 2013 ver.1.06 LC87F1HC8a overview the LC87F1HC8a is an 8-bit microcomputer that, integrates on a single chip a number of hardware features such as 128k-byte flash rom, 16384-byte ram, an on-chip debugger, a 16-bit timer/counter, a 16-bit timer, four 8-bit timers, a base timer serving as a time-of-day clock, 3 ch annels of synchronous sio interface with automatic data transfer capabilities, an asynchronous /synchronous sio interface, a uart inte rface, a full-speed usb interface (host control function), a 12-channel ad converter, 2 channels of 12-bit pwm, a system clock frequency divider, an infrared remote control receiver circ uit, and an interrupt feature. features ? flash rom ? 131072 8 bits ? capable of on-board programming with a wide range of supply voltages: 3.0 to 5.5v ? block-erasable in 128 byte units ? writes data in 2-byte units ? ram ? 16384 9 bits ? package form ? sqfp48(7 7): lead-/halogen-free type ordering number : ena0956e sanyo : sqfp48(7x7) 7.0 7.0 9.0 9.0 0.15 0.5 (1.5) 0.1 1.7max 0.18 0.5 (0.75) 112 13 24 25 36 37 48 package dimensions unit : mm (typ) 3163b ordering number : ena0956e cmos ic 128k-byte from and 16384-byte ram integrated 8-bit 1-chip microcontroller with usb-host controller * this product is licensed from silicon storage technology, inc. (usa).
LC87F1HC8a no.a0956-2/27 ? bus cycle time ? 83.3ns (when cf=12mhz) note: the bus cycle time here refers to the rom read speed. ? minimum instruction cycle time (tcyc) ? 250ns (when cf=12mhz) ? ports ? i/o ports ports whose i/o direction can be designated in 1-bit units 28 (p10 to p17, p20 to p27, p30 to p34, p70 to p73, pwm0, pwm1, xt2) ports whose i/o direction can be designated in 4-bit units 8 (p00 to p07) ? usb ports 2 (uhd+, uhd-) ? dedicated oscillator ports 2 (cf1, cf2) ? input-only port (also used for oscillation) 1 (xt1) ? reset pins 1 ( res ) ? power supply pins 6 (v ss 1 to 3, v dd 1 to 3) ? timers ? timer 0: 16-bit timer/counter with 2 capture registers. mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) 2 channels mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-b it capture registers) + 8-bit counter (with two 8-bit capture registers) mode 2: 16-bit timer with an 8-bit programmabl e prescaler (with two 16-bit capture registers) mode 3: 16-bit counter (with two 16-bit capture registers) ? timer 1: 16-bit timer/counter that supports pwm/toggle outputs mode 0: 8-bit timer with an 8-bit prescal er (with toggle out puts) + 8-bit timer/ counter with an 8-bit pres caler (with toggle outputs) mode 1: 8-bit pwm with an 8-bit prescaler 2 channels mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from lower-order 8 bits) mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (lower-order 8 bits may be used as a pwm output) ? timer 4: 8-bit timer with a 6-bit prescaler ? timer 5: 8-bit timer with a 6-bit prescaler ? timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs) ? timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs) ? base timer 1) the clock is selectable from the subclock (32.768khz crystal oscillation), system clock, and timer 0 prescaler output. 2) interrupts programmable in 5 different time schemes ? sio ? sio0: synchronous serial interface 1) lsb first/msb first mode selectable 2) transfer clock cycle: 4/3 to 512/3 tcyc 3) automatic continuous data transmission (1 to 256 bits, specifiable in 1-bit units) (suspension and resumption of data transmission possible in 1 byte units) ? sio1: 8-bit asynchronous/synchronous serial interface mode 0: synchronous 8-bit serial i/o (2- or 3-wire configuration, 2 to 512 tcyc transfer clocks) mode 1: asynchronous serial i/o (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tcyc baudrates) mode 2: bus mode 1 (start bit, 8 data bits, 2 to 512 tcyc transfer clocks) mode 3: bus mode 2 (start detect, 8 data bits, stop detect) ? sio4: synchronous serial interface 1) lsb first/msb first mode selectable 2) transfer clock cycle: 4/3 to 1020/3 tcyc 3) automatic continuous data transmission (1 to 4096 bytes, specifiable in 1 byte units) (suspension and resumption of data transmission possible in 1 byte units or in word units) 4) auto-start-on-falling-edge function 5) clock polarity selectable 6) crc16 calculator circuit built in
LC87F1HC8a no.a0956-3/27 ? sio9: synchronous serial interface 1) lsb first/msb first mode selectable 2) transfer clock cycle: 4/3 to 1020/3 tcyc 3) automatic continuous data transmission (1 to 4096 bytes, specifiable in 1 byte units) (suspension and resumption of data transmission possible in 1 byte units or word units) 4) auto-start-on-falling-edge function 5) clock polarity selectable 6) crc16 calculator circuit built in ? full duplex uart 1) data length: 7/8/9 bits selectable 2) stop bits: 1 bit (2 bits in continuous transmission mode) 3) baud rate: 16/3 to 8192/3 tcyc ? ad converter: 8 bits 12 channels ? pwm: multifrequency 12-bit pwm 2 channels ? infrared remote control receiver circuit 1) noise rejection function (noise filter time constant: approx. 120 s when the 32.768khz crystal oscillator is selected as the base clock) 2) supports data encoding systems such as ppm (pulse position modulation) and manchester encoding. 3) x'tal hold mode reset function ? usb interface (host control function) 1) compliant with full-speed (12m bps) specifications 2) supports 4 transfer types (control transfer, bulk tr ansfer, interrupt transfer, and isochronous transfer). ? audio interface 1) sampling frequency (fs): 32khz, 44.1khz, 48khz 2) master clock frequency (internal pll): 12.288mhz, 16.9344mhz, 18.432mhz 3) bit clock selectable: 48fs/64fs 4) data bit length: 16/18/20/24 bits 5) lsb first/msb firsts selectable 6) left-justification/right-justification selectable ? watchdog timer ? watchdog timer using external rc circuitry ? interrupt and reset signals selectable ? clock output function 1) can output a clock with a clock rate of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 of the source oscillator clock selected as the system clock. 2) can output the source oscillation clock for the subclock.
LC87F1HC8a no.a0956-4/27 ? interrupts ? 40 sources, 10 vector addresses 1) provides three levels (low (l), high (h), and highest (x )) of multiplex interrupt control. any interrupt requests of the level equal to or lower than th e current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the smallest vector address takes precedence. no. vector address level interrupt source 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l/in t4/uhc bus active/remot e control signal receive 4 0001bh h or l int3/int5/base timer 5 00023h h or l t0h/int6/uhc device connected/uhc disconnected/uhc resume 6 0002bh h or l t1l/t1h /int7/sio9/aif start 7 00033h h or l sio0/uart1 receive 8 0003bh h or l sio1/sio4/uart1 transmit/end of aif 9 00043h h or l adc/t6/t7/uhc-ack/uhc-nak/uhc error/uhc stall 10 0004bh h or l port 0/pwm0/pwm1/t4/t5/uhc-sof/dmcopy ? priority levels x > h > l ? of interrupts of the same level, the one with the smallest vector address takes precedence. ? subroutine stack levels: 8192 levels maximum (the stack is allocated in ram.) ? high-speed multiplication/division instructions ? 16 bits 8 bits (5 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? 16 bits 8 bits (8 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? oscillation and pll circuits ? rc oscillation circuit (internal): for system clock ? cf oscillation circuit: for system clock ? crystal oscillation circuit: for system clock, time-of-day clock ? pll circuit (internal): for usb interface (s ee fig.5) ), audio interface (see fig. 6) ? standby function ? halt mode: halts instruction execution while allowing the peripheral circuits to continue operation. 1) oscillation is not halted automatically. 2) canceled by a system reset or occurrence of an interrupt. ? hold mode: suspends instruction execution and the operation of the peripheral circuits. 1) the pll base clock generator, cf, rc and cr ystal oscillators automatically stop operation. 2) there are four ways of resetting the hold mode. (1) setting the reset pin to the lower level. (2) setting at least one of the int0, int1, int2 , int4, and int5 pins to the specified level (3) having an interrupt source established at port 0 (4) having an bus active interrupt source established in the usb host controll circuit ? x'tal hold mode: suspends instruction execution and the opera tion of the peripheral circu its except the base timer. 1) the pll base clock generator, cf and rc oscillator automatically stop operation. 2) the state of crystal oscillation established wh en the x'tal hold mode is entered is retained. 3) there are six ways of resetting the x'tal hold mode. (1) setting the reset pin to the low level (2) setting at least one of the int0, int1, int2 , int4, and int5 pins to the specified level (3) having an interrupt source established at port 0 (4) having an interrupt source established in the base timer circuit (5) having an bus active interrupt source established in the usb host controll circuit (6) having an interrupt source established in the infrared remote controller receiver circuit
LC87F1HC8a no.a0956-5/27 ? development tools ? on-chip debugger: tcb87- type-b + LC87F1HC8a ? flash rom programming boards package programming boards sqfp48(7 7) w87f55256sq ? recommended eprom programmer maker model supported version device flash support group, inc. (fsg) single programmer af9708/ af9709/af9709b/af9709c (including ando electric co., ltd. models) rev 02.82 or later LC87F1HC8a flash support group, inc. (fsg) + our company(note 1) onboard single/gang programmer af9101/af9103(main body) (fsg models) (note 2) LC87F1HC8a sib87(inter face driver) (our company model) our company single/gang programmer skk/skk typeb (sanyo fws) application version 2.04 or later chip data version 2.11 or later LC87F1HC8 onboard single/gang programmer skk-dbg typeb (sanyo fws) note 1: with the fsg onboard programmer (af9101/af9103) and the serial interface driver (sib87) provided by our company, pc-less standalone onboard programming is possible note 2: depending on programming cond itions, it is necessary to use a dedicat ed programming device and a program. please contact our company or fsg if you have any questions or difficulties regarding this matter.
LC87F1HC8a no.a0956-6/27 pin assignment sqfp48(7 7) ?lead-/halogen-free type? sqfp48 name sqfp48 name 1 p73/int3/t0in/rmin 25 p04/an4/dbgp2 2 res 26 p05/an5/cko/sdat 3 xt1/an10 27 p06/an6/t6o/bclk 4 xt2/an11 28 p07/an7/t7o/lrck 5 v ss 1 29 p20/int4/int6 6 cf1 30 p21/int4 7 cf2 31 p22/int4/so4/ rd 8 v dd 1 32 p23/int4/si4/ wr 9 p10/so0 33 p24/int5/int7/sck4 10 p11/si0/sb0 34 p25/int5/so9/ rd9 11 p12/sck0 35 p26/int5/si9/ wr9 12 p13/so1 36 p27/int5/sck9 13 p14/si1/sb1 37 uhd- 14 p15/sck1 38 uhd+ 15 p16/t1pwml 39 v dd 3 16 p17/t1pwmh/buz 40 v ss 3 17 pwm1/mclki 41 p34/ufilt 18 pwm0/mclko 42 p33/afilt 19 v dd 2 43 p32 20 v ss 2 44 p31/urx1 21 p00/an0 45 p30/utx1 22 p01/an1 46 p70/int0/t0lcp/an8 23 p02/an2/dbgp0 47 p71/int1/t0hcp/an9 24 p03/an3/dbgp1 48 p72/int2/t0in 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 uhd- uhd+ v dd 3 v ss 3 p34/ufilt p33/afilt p32 p31/urx1 p30/utx1 p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in 24 23 22 21 20 19 18 17 16 15 14 13 p03/an3/dbgp1 p02/an2/dbgp0 p01/an1 p00/an0 v ss 2 v dd 2 pwm0/mclko pwm1/mclki p17/t1pwmh/buz p16/t1pwml p15/sck1 p14/si1/sb1 37 38 39 40 41 42 43 44 45 46 47 48 LC87F1HC8a top view p27/int5/sck9 p26/int5/si9/wr9 p25/int5/so9/rd9 p24/int5/int7/sck4 p23/int4/si4/wr p22/int4/so4/rd p21/int4 p20/int4/int6 p07/an7/t7o/lrck p06/an6/t6o/bclk p05/an5/cko/sdat p04/an4/dbgp2 p73/int3/t0in/rmin res xt1/an10 xt2/an11 v ss 1 cf1 cf2 v dd 1 p10/so0 p11/si0/sb0 p12/sck0 p13/so1
LC87F1HC8a no.a0956-7/27 system block diagram interrupt control from standby control clock generator cf x?tal rc ir pla pc bus interface port 0 port 1 acc b register c register alu psw rar ram stack pointer watchdog timer base timer timer 4 pwm1 int0 to int7 noise filter sio0 port 2 usb pll port 7 port 3 adc sio1 timer 0 timer 1 pwm0 timer 5 timer 6 timer 7 uart1 sio4 onchip debugger usb host sio9 audio interface infrared remote control receiver circuit
LC87F1HC8a no.a0956-8/27 pin description pin name i/o description option v ss 1,v ss 2, v ss 3 - - power supply no v dd 1, v dd 2 - + power supply no v dd 3 - usb reference voltage yes port 0 i/o ? 8-bit i/o ports ? i/o specifiable in 4-bit units ? pull-up resistors can be turned on and off in 4-bit units. ? hold reset input ? port 0 interrupt input ? pin functions ad converter input ports: an0 to an7(p00 to p07) onchip debugger pins: dbgp0 to dbgp2(p02 to p04) p05: system clock output/audio interface sdat input/output p06: timer 6 toggle output/audio interface bclk input/output p07: timer 7 toggle output/audio interface lrck input/output yes p00 to p07 port 1 i/o ? 8-bit i/o ports ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p10: sio0 data out put p14: sio1 data input/bus input/output p11: sio0 data input/bus input/out put p15: sio1 clock input/output p12: sio0 clock input/output p16: timer 1 pwml output p13: sio1 data out put p17: timer 1 pwmh output/beeper output yes p10 to p17 port 2 i/o ? 8-bit i/o ports ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p20 to p23: int4 input/hold reset input/timer 1 event in put/timer 0l capture input/ timer 0h capture input p24 to p27: int5 input/hold reset input/timer 1 event in put/timer 0l capture input/ timer 0h capture input p20: int6 input/timer 0l capture 1 input p22: sio4 data input/output/parallel interface rd output p23: sio4 data input/output/parallel interface wr output p24: sio4 clock input/ output/int7 input/timer 0h capture 1 input p25: sio9 data input/output/parallel interface rd9 output p26: sio9 data input/output/parallel interface wr9 output p27: sio9 clock input/output interrupt acknowledge types yes p20 to p27 rising falling rising & falling h level l level int4 enable enable enable disable disable int5 enable enable enable disable disable int6 enable enable enable disable disable int7 enable enable enable disable disable port 3 i/o ? 5-bit i/o ports ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p30: uart1 transmit p31: uart1 receive p33: audio interface pll fi lter pin (see fig. 6.) p34: usb interface pll filter pin (see fig. 5.) yes p30 to p34 continued on next page.
LC87F1HC8a no.a0956-9/27 continued from preceding page. pin name i/o description option port 7 i/o ? 4-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p70: int0 input/hold reset input/time r 0l capture input/watchdog timer output p71: int1 input/hold reset input/timer 0h capture input p72: int2 input/hold reset input/timer 0 event input/timer 0l capture input/ high speed clock counter input p73: int3 input (input with noise filter) /timer 0 event input/timer 0h capture input/ ir remote controller receiver input ad converter input ports: an8(p70), an9(p71) interrupt acknowledge types no p70 to p73 rising falling rising & falling h level l level int0 enable enable disable enable enable int1 enable enable disable enable enable int2 enable enable enable disable disable int3 enable enable enable disable disable pwm0 pwm1 i/o pwm0, pwm1 output port general-purpose input port ? pin functions pwm0: audio interface master clock output pwm1: audio interface master clock input no uhd- i/o usb data i/o pin uhd-/general-purpose i/o port no uhd+ i/o usb data i/o pin uhd+/general-purpose i/o port no res input reset pin no xt1 input ? 32.768khz crystal oscillator input ? pin functions general-purpose input port ad converter input ports: an10 must be connected to v dd 1 when not to be used. no xt2 i/o ? 32.768khz crystal oscillator output ? pin functions general-purpose i/o ad converter input port: an11 must be set for oscillation and kept open if not to be used. no cf1 input ceramic/crystal resonator input no cf2 output ceramic/crystal resonator output no
LC87F1HC8a no.a0956-10/27 port output types the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port name option selected in units of option type output type pull-up resistor p00 to p07 1 bit 1 cmos programmable (note 1) 2 nch-open drain no p10 to p17 p20 to p27 p30 to p34 1 bit 1 cmos programmable 2 nch-open drain programmable p70 - no nch-open drain programmable p71 to p73 - no cmos programmable pwm0, pwm1 - no cmos no uhd+, uhd- - no cmos no xt1 - no input only no xt2 - no 32.768khz crystal resonator output (n channel open drain when in general-purpose output mode) no note 1: programmable pull-up resistors for port 0 are controlled in 4 bit units (p00 to 03, p04 to 07). power pin treatment connect the ic as shown below to minimize the noise input to the v dd 1 pin. and extend the backup period. be sure to electrically short the v ss 1, v ss 2, and v ss 3 pins. example 1: when the microcontroller is in the backup state in the hold mode, th e power to sustain the high level of output ports is supplied by their backup capacitors. example 2: the high level output at ports is not sustained and unstable in the hold backup mode. v ss 1 v ss 2 v ss 3 v dd 1 v dd 2 v dd 3 power supply for backup lsi lsi v ss 1v ss 2v ss 3 v dd 1 v dd 2 v dd 3 power supply for backup
LC87F1HC8a no.a0956-11/27 usb reference power option when a voltage 4.5 to 5.5v is supplied to v dd 1 and the internal usb reference voltage circuit is activated, the reference voltage for usb port output is generated. the ac tive/inactive state of the reference voltage circuit can be switched by option select. the procedure for marking the option selection is described below. (1) (2) (3) (4) option settings usb regulator use use use nonuse usb regulator at hold mode use nonuse nonuse nonuse usb regulator at halt m ode use nonuse use nonuse reference voltage circuit state normal mode active active active inactive hold mode active inactive inactive inactive halt mode active inactive active inactive ? when the usb reference voltage circuit is made inactive, th e level of the reference voltage for usb port output is equal to v dd 1. ? selection (2) or (3) can be used to set the reference voltage circuit inactive in hold or halt mode. ? when the reference voltage circuit is activated, the current drain increases by approximately 100 a compared with when the reference voltage circuit is inactive. example 1: v dd 1=v dd 2=3.3v ? inactivating the reference voltage circuit (selection (4)). ? connecting v dd 3 to v dd 1 and v dd 2. example 2: v dd 1=v dd 2=5.0v ? activating the reference voltage circuit (selection (1)). ? isolating v dd 3 from v dd 1 and v dd 2, and connecting capacitor between v dd 3 and v ss . v ss 1 v ss 2v ss 3 v dd 1 v dd 2 v dd 3 power supply 3.3v for backup lsi uhd+ uhd- ufilt 15k to usb connector 33 5pf 0 2.2 2.2 to usb connector 33 5pf 2.2 f 0.1
LC87F1HC8a no.a0956-12/27 absolute maximum ratings at ta = 25c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit maximum supply voltage v dd max v dd 1, v dd 2, v dd 3 v dd 1= v dd 2= v dd 3 -0.3 +6.5 v input voltage v i (1) xt1, cf1 -0.3 v dd +0.3 input/output voltage v io (1) ports 0, 1, 2, 3, 7 pwm0, pwm1 xt2 -0.3 v dd +0.3 high level output current peak output current ioph(1) ports 0, 1, 2 ? when cmos output type is selected ? per 1 applicable pin -10 ma ioph(2) pwm0, pwm1 per 1 applicable pin -20 ioph(3) port 3 p71 to p73 ? when cmos output type is selected ? per 1 applicable pin -5 average output current (note 1-1) iomh(1) ports 0, 1, 2 ? when cmos output type is selected ? per 1 applicable pin -7.5 iomh(2) pwm0, pwm1 per 1 applicable pin -15 iomh(3) port 3 p71 to p73 ? when cmos output type is selected ? per 1 applicable pin -3 total output current ioah(1) ports 0, 2 to tal current of all applicable pins -25 ioah(2) port 1 pwm0, pwm1 total current of all applicable pins -25 ioah(3) ports 0, 1, 2 pwm0, pwm1 total current of all applicable pins -45 ioah(4) port 3 p71 to p73 total current of all applicable pins -10 ioah(5) uhd+, uhd- total current of all applicable pins -25 low level output current peak output current iopl(1) p02 to p07 ports 1, 2 pwm0, pwm1 per 1 applicable pin 20 iopl(2) p00, p01 per 1 applicable pin 30 iopl(3) ports 3, 7 xt2 per 1 applicable pin 10 average output current (note 1-1) ioml(1) p02 to p07 ports 1, 2 pwm0, pwm1 per 1 applicable pin 15 ioml(2) p00, p01 per 1 applicable pin 20 ioml(3) ports 3, 7 xt2 per 1 applicable pin 7.5 total output current ioal(1) ports 0, 2 total current of all applicable pins 45 ioal(2) port 1 pwm0, pwm1 total current of all applicable pins 45 ioal(3) ports 0, 1, 2 pwm0, pwm1 total current of all applicable pins 80 ioal(4) ports 3, 7 xt2 total current of all applicable pins 15 ioal(5) uhd+, uhd- total current of all applicable pins 25 allowable power dissipation pd max sqfp48(7 7) ta=-40 to +85 c 140 mw operating ambient temperature topr -40 +85 c storage ambient temperature tstg -55 +125 note 1-1: the average output current is an average of current values measured over 100ms intervals. stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
LC87F1HC8a no.a0956-13/27 allowable operating conditions at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit operating supply voltage (note 2-1) v dd (1) v dd 1=v dd 2=v dd 3 0.245s tcyc 200s 3.0 5.5 v 0.490s tcyc 200s except in onboard programming mode 2.7 5.5 memory sustaining supply voltage vhd v dd 1=v dd 2=v dd 3 ram and register contents sustained in hold mode. 2.0 5.5 high level input voltage v ih (1) port 0, 1, 2, 3 p71 to p73 p70 port input/ interrupt side pwm0, pwm1 2.7 to 5.5 0.3v dd +0.7 v dd v ih (2) port 70 watchdog timer side 2.7 to 5.5 0.9v dd v dd v ih (3) xt1, xt2, cf1, res 2.7 to 5.5 0.75v dd v dd low level input voltage v il (1) port 1, 2, 3 p71 to p73 p70 port input/ interrupt side 4.0 to 5.5 v ss 0.1v dd +0.4 v il (2) 2.7 to 4.0 v ss 0.2v dd v il (3) port 0 pwm0, pwm1 4.0 to 5.5 v ss 0.15v dd +0.4 v il (4) 2.7 to 4.0 v ss 0.2v dd v il (5) port 70 watchdog timer side 2.7 to 5.5 v ss 0.8v dd -1.0 v il (6) xt1, xt2, cf1, res 2.7 to 5.5 v ss 0.25v dd instruction cycle time (note 2-2) tcyc 3.0 to 5.5 0.245 200 s except for onboard programming mode 2.7 to 5.5 0.490 200 external system clock frequency fexcf(1) cf1 ? cf2 pin open ? system clock frequency division ratio=1/1 ? external system clock duty =50 5% 3.0 to 5.5 0.1 12 mhz ? cf2 pin open ? system clock frequency division ratio=1/1 ? external system clock duty =50 5% 2.7 to 5.5 0.1 6 oscillation frequency range (note 2-3) fmcf(1) cf1, cf2 when 12m hz ceramic oscillation see fig. 1. 3.0 to 5.5 12 mhz fmcf(2) cf1, cf2 when 6m hz ceramic oscillation see fig. 1. 2.7 to 5.5 6 fmrc internal rc oscillation 2.7 to 5.5 0.3 1.0 2.0 fsx?tal xt1, xt2 32.768khz crystal oscillation see fig. 2. 2.7 to 5.5 32.768 khz note 2-1: v dd must be held greater than or equal to 3.0v in the flash rom onboard programming mode. note 2-2: relationship between tcyc and oscillation frequency is 3/fmcf at a division ratio of 1/1 and 6/fmcf at a division ratio of 1/2. note 2-3: see tables 1 and 2 for the oscillation constants.
LC87F1HC8a no.a0956-14/27 electrical characteristics at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit high level input current i ih (1) ports 0, 1, 2, 3 port 7 res pwm0, pwm1 uhd+, uhd- output disabled pull-up resistor off v in =v dd (including output tr's off leakage current) 2.7 to 5.5 1 a i ih (2) xt1, xt2 input port configuration v in =v dd 2.7 to 5.5 1 i ih (3) cf1 v in =v dd 2.7 to 5.5 15 low level input current i il (1) ports 0, 1, 2, 3 port 7 res pwm0, pwm1 uhd+, uhd- output disabled pull-up resistor off v in =v ss (including output tr's off leakage current) 2.7 to 5.5 -1 i il (2) xt1, xt2 input port configuration v in =v ss 2.7 to 5.5 -1 i il (3) cf1 v in =v ss 2.7 to 5.5 -15 high level output voltage v oh (1) ports 0, 1, 2, 3 p71 to p73 i oh =-1ma 4.5 to 5.5 v dd -1 v v oh (2) i oh =-0.4ma 3.0 to 5.5 v dd -0.4 v oh (3) i oh =-0.2ma 2.7 to 5.5 v dd -0.4 v oh (4) pwm0, wm1 p05 to p07 (note 3-1) i oh =-10ma 4.5 to 5.5 v dd -1.5 v oh (5) i oh =-1.6ma 3.0 to 5.5 v dd -0.4 v oh (6) i oh =-1ma 2.7 to 5.5 v dd -0.4 low level output voltage v ol (1) p00, p01 i ol =30ma 4.5 to 5.5 1.5 v ol (2) i ol =5ma 3.0 to 5.5 0.4 v ol (3) i ol =2.5ma 2.7 to 5.5 0.4 v ol (4) ports 0, 1, 2 pwm0, pwm1 xt2 i ol =10ma 4.5 to 5.5 1.5 v ol (5) i ol =1.6ma 3.0 to 5.5 0.4 v ol (6) i ol =1ma 2.7 to 5.5 0.4 v ol (7) ports 3, 7 i ol =1.6ma 3.0 to 5.5 0.4 v ol (8) i ol =1ma 2.7 to 5.5 0.4 pull-up resistance rpu(1) ports 0, 1, 2, 3 port 7 v oh =0.9v dd 4.5 to 5.5 15 35 80 k rpu(2) 2.7 to 5.5 18 50 150 hysteresis voltage vhys res port 1, 2, 3, 7 2.7 to 5.5 0.1v dd v pin capacitance cp all pins for pins other than that under test: v in =v ss f=1mhz ta=25 c 2.7 to 5.5 10 pf note 3-1: when the cko system clock output function (p05) or audio interface ou tput function (p05 to p07) is used.
LC87F1HC8a no.a0956-15/27 serial i/o characteristics at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v 1. sio0 serial i/o characteristics (note 4-1-1) parameter symbol pin/ remarks conditions specification v dd [v] min typ max unit serial clock input clock frequency tsck(1) sck0(p12) see fig. 8. 2.7 to 5.5 2 tcyc low level pulse width tsckl(1) 1 high level pulse width tsckh(1) 1 tsckha(1a) ? continuous data transfer mode ? usb, aif, sio4, sio9, and dmcopy not used at the same time. ? see fig. 8. ? (note 4-1-2) 4 tsckha(1b) ? continuous data transfer mode ? usb used at the same time. ? aif, sio4, sio9, and dmcopy not used at the same time. ? see fig. 8. ? (note 4-1-2) 7 tsckha(1c) ? continuous data transfer mode ? usb, aif, sio4, sio9, and dmcopy used at the same time. ? see fig. 8. ? (note 4-1-2) 9 output clock frequency tsck(2) sck0(p12) ? when cmos output type is selected ? see fig. 8. 2.7 to 5.5 4/3 low level pulse width tsckl(2) 1/2 tsck high level pulse width tsckh(2) 1/2 tsckha(2a) ? continuous data transfer mode ? usb, aif, sio4, sio9, and dmcopy not used at the same time. ? when cmos output type is selected ? see fig. 8. tsckh(2) +2tcyc tsckh(2) + (10/3)tcyc tcyc tsckha(2b) ? continuous data transfer mode ? usb used at the same time. ? aif, sio4, sio9, and dmcopy not used at the same time. ? when cmos output type is selected. ? see fig. 8. tsckh(2) +2tcyc tsckh(2) + (19/3)tcyc tsckha(2c) ? continuous data transfer mode ? usb, aif, sio4, sio9, and dmcopy used at the same time ? when cmos output type is selected ? see fig. 8. tsckh(2) +2tcyc tsckh(2) + (25/3)tcyc note 4-1-1: these specifications are theoretical values. ma rgins must be allowed according to the actual operating conditions. note 4-1-2: in an application where the serial clock input is to be used in the continuous data transfer mode, the time from si0run being set when serial clock is high to th e falling edge of the first serial clock must be longer than tsckha. continued on next page.
LC87F1HC8a no.a0956-16/27 continued from preceding page. parameter symbol pin/ remarks conditions specification v dd [v] min typ max unit serial input data setup time tsdi(1) sb0(p11), si0(p11) ? must be specified with respect to rising edge of sioclk. ? see fig. 8. 2.7 to 5.5 0.03 s data hold time thdi(1) 0.03 serial output input clock output delay time tdd0(1) so0(p10), sb0(p11) ? continuous data transfer mode ? (note 4-1-3) 2.7 to 5.5 (1/3)tcyc +0.05 tdd0(2) ? synchronous 8-bit mode ? (note 4-1-3) 1tcyc +0.05 output clock tdd0(3) (note 4-1-3) (1/3)tcyc +0.05 note 4-1-3: must be specified with respect to falling edge of sioclk. must be specified as the time to the beginning of output state change in open drain output mode. see fig. 8. 2. sio1 serial i/o characteristics (note 4-2-1) parameter symbol pin/ remarks conditions specification v dd [v] min typ max unit serial clock input clock frequency tsck(3) sck1(p15) see fig. 8. 2.7 to 5.5 2 tcyc low level pulse width tsckl(3) 1 high level pulse width tsckh(3) 1 output clock frequency tsck(4) sck1(p15) ? when cmos output type is selected ? see fig. 8. 2.7 to 5.5 2 low level pulse width tsckl(4) 1/2 tsck high level pulse width tsckh(4) 1/2 serial input data setup time tsdi(2) sb1(p14), si1(p14) ? must be specified with respect to rising edge of sioclk. ? see fig. 8. 2.7 to 5.5 0.03 s data hold time thdi(2) 0.03 serial output output delay time tdd0(4) so1(p13), sb1(p14) ? must be specified with respect to falling edge of sioclk. ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig. 8. 2.7 to 5.5 (1/3)tcyc +0.05 note 4-2-1: these specifications are theoretical values. ma rgins must be allowed according to the actual operating conditions.
LC87F1HC8a no.a0956-17/27 3. sio4 serial i/o characteristics (note 4-3-1) parameter symbol pin/ remarks conditions specification v dd [v] min typ max unit serial clock input clock frequency tsck(5) sck4(p24) see fig. 8. 2.7 to 5.5 2 tcyc low level pulse width tsckl(5) 1 high level pulse width tsckh(5) 1 tsckha(5a) ? usb, sio0 continuous transfer mode, aif, sio9, and dmcopy not used at the same time. ? see fig. 8. ? (note 4-3-2) 4 tsckha(5b) ? usb used at the same time ? sio0 continuous transfer mode, aif, sio9, dmcopy not used at the same time. ? see fig. 8. ? (note 4-3-2) 7 tsckha(5c) ? usb, sio0 continuous transfer mode, sio9, and dmcopy used at the same time. ? aif not used at the same time. ? see fig. 8. ? (note 4-3-2) 12 output clock frequency tsck(6) sck4(p24) ? when cmos output type is selected. ? see fig. 8. 2.7 to 5.5 4/3 low level pulse width tsckl(6) 1/2 tsck high level pulse width (note 4-3-3) tsckh(6) 1/2 tsckha(6a) ? usb, sio0 continuous transfer mode, aif, sio9, and dmcopy not used at the same time. ? when cmos output type is selected. ? see fig. 8. tsckh(6) + (5/3)tcyc tsckh(6) + (10/3)tcyc tcyc tsckha(6b) ? usb used at the same time. ? sio0 continuous transfer mode, aif, sio9, and dmcopy not used at the same time. ? when cmos output type is selected. ? see fig. 8. tsckh(6) + (5/3)tcyc tsckh(6) + (19/3)tcyc tsckha(6c) ? usb, sio0 continuous transfer mode, sio9, and dmcopy used at the same time. ? aif not used at the same time. ? when cmos output type is selected. ? see fig. 8. tsckh(6) + (5/3)tcyc tsckh(6) + (34/3)tcyc note 4-3-1: these specifications are theoretical values. ma rgins must be allowed according to the actual operating conditions. note 4-3-2: in an application where the serial clock input is to be used in the continuous data transfer mode, the period from the time si4run is set with the serial clock set high to the falling edge of the first serial clock must be longer than tsckha. note 4-3-3: when using the serial clock output, make sure that the load at the sck4 (p 24) pin meets the following conditions: clock rise time tsckr < 0.037 s (see figure 12.) at ta=+25 c, v dd =3.3v continued on next page.
LC87F1HC8a no.a0956-18/27 continued from preceding page. parameter symbol pin/ remarks conditions specification v dd [v] min typ max unit serial input data setup time tsdi(3) so4(p22), si4(p23) ? must be specified with respect to falling edge of sioclk. ? see fig. 8 2.7 to 5.5 0.03 s data hold time thdi(3) 0.03 serial output output delay time tdd0(5) so4(p22), si4(p23) ? must be specified with respect to rising edge of sioclk. ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig. 8. 2.7 to 5.5 (1/3)tcyc +0.05 4. sio9 serial i/o characteristics (note 4-4-1) parameter symbol pin/ remarks conditions specification v dd [v] min typ max unit serial clock input clock frequency tsck(7) sck9(p27) see fig. 8. 2.7 to 5.5 2 tcyc low level pulse width tsckl(7) 1 high level pulse width tsckh(7) 1 tsckha(7a) ? usb, sio0 continuous transfer mode, aif, sio4 and dmcopy not used at the same time. ? see fig. 8. ? (note 4-4-2) 4 tsckha(7b) ? usb used at the same time. ? sio0 continuous transfer mode, aif, sio4, and dmcopy not used at the same time. ? see fig. 8. ? (note 4-4-2) 7 tsckha(7c) ? usb, sio0 continuous transfer mode, sio4 and dmcopy used at the same time. ? aif not used at the same time. ? see fig. 8. ? (note 4-4-2) 15 note 4-4-1: these specifications are theoretical values. ma rgins must be allowed according to the actual operating conditions. note 4-4-2: in an application where the serial clock input is to be used in the continuous data transfer mode, the period from the time si9run is set with the serial clock set high to the falling edge of the first serial clock must be longer than tsckha. continued on next page
LC87F1HC8a no.a0956-19/27 continued from preceding page parameter symbol pin/ remarks conditions specification v dd [v] min typ max unit serial clock output clock frequency tsck(8) sck9(p27) ? when cmos output type is selected. ? see fig. 8. 2.7 to 5.5 4/3 tcyc low level pulse width tsckl(8) 1/2 tsck high level pulse width (note 4-4-3) tsckh(8) 1/2 tsckha(8a) ? usb, sio0 continuous transfer mode, aif sio4 dmcopy not used at the same time. ? when cmos output type is selected. ? see fig. 8. tsckh(8) + (5/3)tcyc tsckh(8) + (10/3)tcyc tcyc tsckha(8b) ? usb used at the same time. ? sio0 continuous transfer mode, aif, sio4, and dmcopy not used at the same time. ? when cmos output type is selected ? see fig. 8. tsckh(8) + (5/3)tcyc tsckh(8) + (19/3)tcyc tsckha(8c) ? usb, sio0 continuous transfer mode , sio4, and dmcopy used at the same time. ? aif not used at the same time. ? when cmos output type is selected. ? see fig. 8. tsckh(8) + (5/3)tcyc tsckh(8) + (43/3)tcyc serial input data setup time tsdi(4) so9(p25), si9(p26) ? must be specified with respect to rising edge of sioclk. ? see fig. 8. 2.7 to 5.5 0.03 s data hold time thdi(4) 0.03 serial output output delay time tddo(6) so9(p25), si9(p26) ? must be specified with respect to falling edge of sioclk. ? must be specified as the time to the beginning of output state change in open drain output mode ? see fig. 8. 2.7 to 5.5 (1/3)tcyc +0.05 note 4-4-3: when using the serial clock output, make sure that the load at the sck9 (p 27) pin meets the following conditions: clock rise time tsckr < 0.037 s (see figure 12.) at ta=+25 c, v dd =3.3v
LC87F1HC8a no.a0956-20/27 pulse input conditions at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit high/low level pulse width tp1h(1) tp1l(1) int0(p70), int1(p71), int2(p72), int4(p20 to p23), int5(p24 to p27), int6(p20), int7(p24) ? interrupt source flag can be set. ? event inputs for timer 0 or 1 are enabled. 2.7 to 5.5 1 tcyc tpih(2) tpil(2) int3(p73) when noise filter time constant is 1/1 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 2 tpih(3) tpil(3) int3(p73) when noise filter time constant is 1/32 ? interrupt source flag can be set. ? event inputs for timer 0 are nabled. 2.7 to 5.5 64 tpih(4) tpil(4) int3(p73) when noise filter time constant is 1/128 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 256 tpil(5) rmin(p73) recognized by the infrared remote control receiver circuit as a signal 2.7 to 5.5 4 rmck (note 5-1) tpil(6) res resetting is enabled. 2.7 to 5.5 200 s note 5-1: represents the period of the reference clock (1 tc yc to 128 tcyc or the source frequency of the subclock) for the infrared remote control receiver circuit. ad converter characteristics at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit resolution n an0(p00) to an7(p07), an8(p70), an9(p71), an10(xt1), an11(xt2) 3.0 to 5.5 8 bit absolute accuracy et (note 6-1) 3.0 to 5.5 1.5 lsb conversion time tcad ad conversion time=32 tcyc (when adcr2=0) (note 6-2) 4.5 to 5.5 15.68 (tcyc= 0.490s) 97.92 (tcyc= 3.06s) s 3.0 to 5.5 23.52 (tcyc= 0.735s) 97.92 (tcyc= 3.06s) ad conversion time=64 tcyc (when adcr2=1) (note 6-2) 4.5 to 5.5 18.82 (tcyc= 0. 294s) 97.92 (tcyc= 1.53s) 3.0 to 5.5 47.04 (tcyc= 0.735s) 97.92 (tcyc= 1.53s) analog input voltage range vain 3.0 to 5.5 v ss v dd v analog port input current iainh vain=v dd 3.0 to 5.5 1 a iainl vain=v ss 3.0 to 5.5 -1 note 6-1: the quantization error ( 1/2lsb) is excluded fro m the absolute accuracy. note 6-2: the conversion time refers to the period from the ti me when an instruction for star ting a conversion process is issued to the time the conversion re sults register(s) are loaded with a complete digital conversion value corresponding to the analog input value.
LC87F1HC8a no.a0956-21/27 consumption current characteristics at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pin/ remarks conditions specification v dd [v] min typ max unit normal mode consumption current (note 7-1) iddop(1) v dd 1 =v dd 2 =v dd 3 ? fmcf=12mhz ceramic oscillation mode ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal pll oscillation stopped ? internal rc oscillation stopped ? usb circuit stopped ? 1/1 frequency division ratio 4.5 to 5.5 9.8 24 ma iddop(2) 3.0 to 3.6 5.7 14 iddop(3) ? fmcf=12mhz ceramic oscillation mode ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal pll oscillation mode active ? internal rc oscillation stopped ? usb circuit active ? 1/1 frequency division ratio 4.5 to 5.5 15 35 iddop(4) 3.0 to 3.6 7.7 20 iddop(5) ? fmcf=12mhz ceramic oscillation mode ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 6mhz side ? internal rc oscillation stopped ? 1/2 frequency division ratio 4.5 to 5.5 6.7 16 iddop(6) 3.0 to 3.6 3.9 9.0 iddop(7) 2.7 to 3.0 3.2 7.3 iddop(8) ? fmcf=0hz(oscillation stopped) ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to internal rc oscillation. ? 1/2 frequency division ratio 4.5 to 5.5 0.72 3.4 iddop(9) 3.0 to 3.6 0.41 1.9 iddop(10) 2.7 to 3.0 0.35 1.5 iddop(11) ? fmcf=0hz(oscillation stopped) ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to crystal oscillation. (32.768khz) ? internal rc oscillation stopped ? 1/2 frequency division ratio 4.5 to 5.5 45 184 a iddop(12) 3.0 to 3.6 18 65 iddop(13) 2.7 to 3.0 14 47 halt mode consumption current (note7-1) iddhalt(1) ? halt mode ? fmcf=12mhz ceramic oscillation mode ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal pll oscillation stopped ? internal rc oscillation stopped ? usb circuit stopped ? 1/1 frequency division ratio 4.5 to 5.5 4.9 12 ma iddhalt(2) 3.0 to 3.6 2.7 6.4 iddhalt(3) ? halt mode ? fmcf=12mhz ceramic oscillation mode ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal pll oscillation mode active ? internal rc oscillation stopped ? usb circuit active ? 1/1 frequency division ratio 4.5 to 5.5 9.5 23 iddhalt(4) 3.0 to 3.6 4.7 12 iddhalt(5) ? halt mode ? fmcf=12mhz ceramic oscillation mode ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 6mhz side ? internal rc oscillation stopped ? 1/2 frequency division ratio 4.5 to 5.5 3.0 7.3 iddhalt(6) 3.0 to 3.6 1.6 3.8 iddhalt(7) 2.7 to 3.0 1.3 2.9 iddhalt(8) ? halt mode ? fmcf=0hz(oscillation stopped) ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to internal rc oscillation. ? 1/2 frequency division ratio 4.5 to 5.5 0.41 2.0 iddhalt(9) 3.0 to 3.6 0.20 0.95 iddhalt(10) 2.7 to 3.0 0.17 0.70 note 7-1: the consumption current value includes none of the cu rrents that flow into the output tr and internal pull-up resistors. continued on next page.
LC87F1HC8a no.a0956-22/27 continued from preceding page. parameter symbol pin/ remarks conditions specification v dd [v] min typ max unit halt mode consumption current (note 7-1) iddhalt(11) v dd 1 =v dd 2 =v dd 3 ? halt mode ? fmcf=0mhz (oscillation stopped) ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to crystal oscillation. (32.768khz) ? internal rc oscillation stopped ? 1/2 frequency division ratio 4.5 to 5.5 31 132 a iddhalt(12) 3.0 to 3.6 9.1 39 iddhalt(13) 2.7 to 3.0 6.3 27 hold mode consumption current iddhold(1) v dd 1 ? hold mode ? cf1=v dd or open (external clock mode) 4.5 to 5.5 0.14 39 iddhold(2) 3.0 to 3.6 0.04 19 iddhold(3) 2.7 to 3.0 0.04 17 timer hold mode consumption current iddhold(4) ? timer hold mode ? cf1=v dd or open (external clock mode) ? fsx?tal=32.768khz crystal oscillation mode 4.5 to 5.5 25 115 iddhold(5) 3.0 to 3.6 6.0 32 iddhold(6) 2.7 to 3.0 3.7 20 note 7-1: the consumption current value includes none of the cu rrents that flow into the output tr and internal pull-up resistors usb characteristics and timing at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol conditions specification min typ max unit high level output v oh(usb) ? 15k ? 5% to gnd 2.8 3.6 v low level output v ol(usb) ? 1.5k ? 5% to 3.6v 0.0 0.3 v output signal crossover voltage v crs 1.3 2.0 v differential input sensitivity v di ? ? (uhd+)-(uhd-) ? 0.2 v differential input common mode range v cm 0.8 2.5 v high level input v ih(usb) 2.0 v low level input v il(usb) 0.8 v usb data rise time t r ? r s =33 , c l =50pf 4 20 ns usb data fall time t f ? r s =33 , c l =50pf 4 20 ns f-rom programming characteristics at ta = +10c to +55c, v ss 1 = 0v parameter symbol pin/ remarks conditions specification v dd [v] min typ max unit onboard programming current iddfw(1) v dd 1 ? excluding power dissipation in the microcontroller block 3.0 to 5.5 5 10 ma programming time tfw(1) ? erase operation 3.0 to 5.5 20 30 ms tfw(2) ? write operation 40 60 s
LC87F1HC8a no.a0956-23/27 characteristics of a sample main system clock oscillation circuit given below are the characteristics of a sample main system clock oscillation circuit that are measured using a our designated oscillation characteristics evaluation board and exte rnal components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 1 shows the characteristics of a oscillati on circuit when usb host function is not used. if usb host function is to be used, it is absolutely recomme nded to use an oscillator that satisfies the precision and stability according to the usb standards. table 1 characteristics of a sample main system clock oscillator circuit with a ceramic oscillator nominal frequency vendor name oscillator name circuit constant operating voltage range [v] oscillation stabilization time remarks c1 [pf] c2 [pf] rd1 [ ] typ [ms] max [ms] 6mhz murata cstcr6m00gh5l**-r0 ( 39) (39) 1k 2.7 to 5.5 0.1 0.5 c1 and c2 integrated smd type 8mhz murata cstce8m00gh5l**-r0 (33) (33) 470 3.0 to 5.5 0.1 0.5 10mhz murata cstce10m0gh5l**-r0 (33) (33) 330 3.0 to 5.5 0.1 0.5 12mhz murata cstce12m0gh5l**-r0 (33) (33) 330 3.0 to 5.5 0.1 0.5 the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized in the following cases (see figure 4): ? till the oscillation gets stabilized after v dd goes above the operating voltage lower limit. ? till the oscillation gets stabilized after the instruction fo r starting the main clock oscillation circuit is executed ? till the oscillation gets stabilized after the hold mode is reset. ? till the oscillation gets stabilized after the x'tal hold mode is reset with cfstop (ocr register, bit 0) set to 0 characteristics of a sample subs ystem clock oscillator circuit given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a our designated oscillation characteristics evaluation board and exte rnal components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 2 characteristics of a sample subsystem cl ock oscillator circuit with a crystal oscillator nominal frequency vendor name oscillator name circuit constant operating voltage range [v] oscillation stabilization time remarks c3 [pf] c4 [pf] rf [ ] rd2 [ ] typ [s] max [s] 32.768khz epson toyocom mc-306 18 18 open 560k 2.7 to 5.5 1.1 3.0 applicable cl value=12.5pf smd type the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized in the following cases (see figure 4): ? till the oscillation gets stabilized after the instruction fo r starting the subclock oscillation circuit is executed ? till the oscillation gets stabilized after the hold mode is reset with extosc (ocr register, bit 6) set to 1 note: the components that are in volved in oscillation should be placed as close to the ic an d to one another as possible because they are vulnerable to the influences of the circuit pattern. figure 1 cf oscillator circuit figure 2 crystal oscillator circuit rf rd2 xt1 xt2 c4 x?tal c3 rd1 cf1 cf2 c2 cf c1
LC87F1HC8a no.a0956-24/27 figure 3 ac timing measurement point reset time and oscillation stabilization time hold reset signal and oscillation stabilization time figure 4 oscillation stabilization time 0.5v dd internal rc oscillation cf1,cf2 xt1, xt2 operating mode hold reset signal hold reset signal valid tmscf tmsx?tal hold halt power supply res internal rc oscillation cf1, cf2 xt1, xt2 operating mode reset time tmscf tmsx?tal unpredictable reset instruction execution v dd operating v dd lower limit gnd
LC87F1HC8a no.a0956-25/27 figure 5 external filter circuit for th e internal usb-dedicated pll circuit figure 6 external filter circuit for audio interface (used with in ternal pll circuit) figure 7 usb port peripheral circuit when using the internal pll circuit to generate the 48mhz clock for usb , it is necessary to connect a filter circuit such to the p34/ufilt pin such as that shown in the left fig. rd 0k cd 2.2 uhd- uhd+ 5pf 33 15k 15k it?s necessary to adjust the circuit constant of the usb port peripheral circuit for each mounting board. to generate the master clock for the audio interface using the intern al pll circuit, it is necessary to connect a filter circuit to the p33/afilt pin that is shown in the left fig. rd 150 cd 4.7 f p33/afilt + - cp 1 f + -
LC87F1HC8a no.a0956-26/27 figure 8 reset circuit figure 9 serial input/output waveform c res v dd r res res note: determine the value of c res and r res so that the reset signal is present for a period of 200s after the supply voltage goes beyond the lower limit of the ic's operating voltage. data ram transfer period (sio0, 4, 9 only) data ram transfer period (sio0, 4, 9 only) di0 di7 di2 di3 di4 di5 di6 di8 do0 do7 do2 do3 do4 do5 do6 do8 di1 do1 sioclk: datain: dataout: dataout: datain: sioclk: dataout: datain: sioclk: tsck tsckl tsckh thdi tsdi tddo tsckl tsckha thdi tsdi tddo
LC87F1HC8a no.a0956-27/27 figure 10 pulse input timing signal waveform figure 11 usb data signal timing and voltage level figure 12 serial clock output timing signal waveform ps tpil tpih t r t r d+ d- 10% 10% 90% 90% v oh v crs v ol v ih (1) min.=0.3v dd +0.7v tsckr tsckr: defined as the time period from the time the state of the output starts changing till the time it reaches the minimum value of v ih (1). on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.

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